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<DIV id="content" onclick="hideTocList()"><PRE>
<A name="pn230314231227"></A><B><U><big>pn230314231227</big></U></B>
#Start recording tcl command: 3/14/2023 22:06:44
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_set_impl_opt -impl "impl_1" -rem "top"
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_syn_sim_source -src "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.v" SynthesisAndSimulate
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_remove_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/f_spi.pdc"
#Stop recording: 3/14/2023 23:12:27



<A name="pn230314231717"></A><B><U><big>pn230314231717</big></U></B>
#Start recording tcl command: 3/14/2023 22:04:29
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_set_impl_opt -impl "impl_1" "top" "awg"
prj_set_impl_opt -impl "impl_1" "top" "awg.v"
#Stop recording: 3/14/2023 23:17:17



<A name="pn230314232003"></A><B><U><big>pn230314232003</big></U></B>
#Start recording tcl command: 3/14/2023 23:12:38
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc"
prj_enable_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
#Stop recording: 3/14/2023 23:20:03



<A name="pn230314232035"></A><B><U><big>pn230314232035</big></U></B>
#Start recording tcl command: 3/14/2023 23:20:13
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
#Stop recording: 3/14/2023 23:20:35



<A name="pn230315021019"></A><B><U><big>pn230315021019</big></U></B>
#Start recording tcl command: 3/14/2023 23:21:16
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_remove_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc"
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc"
prj_enable_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/awg.pdc"
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
#Stop recording: 3/15/2023 02:10:19



<A name="pn230315110431"></A><B><U><big>pn230315110431</big></U></B>
#Start recording tcl command: 3/15/2023 10:17:35
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/sin/sin.ipx"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/square/square.ipx"
#Stop recording: 3/15/2023 11:04:31



<A name="pn230315150526"></A><B><U><big>pn230315150526</big></U></B>
#Start recording tcl command: 3/15/2023 11:04:41
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_remove_source "C:/Users/zyx/my_designs/awg_fpga/sin/sin.ipx"
prj_remove_source "C:/Users/zyx/my_designs/awg_fpga/square/square.ipx"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/sine/sine.ipx"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/square/square.ipx"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/triangle/triangle.ipx"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/source/impl_1/DDS.v"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Synthesis -impl impl_1
prj_run Map -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Synthesis -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
#Stop recording: 3/15/2023 15:05:26



<A name="pn230315182402"></A><B><U><big>pn230315182402</big></U></B>
#Start recording tcl command: 3/15/2023 15:27:33
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/square/rtl/square.v"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/sine/rtl/sine.v"
prj_add_source "C:/Users/zyx/my_designs/awg_fpga/triangle/rtl/triangle.v"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
#Stop recording: 3/15/2023 18:24:02



<A name="pn230315203107"></A><B><U><big>pn230315203107</big></U></B>
#Start recording tcl command: 3/15/2023 18:33:36
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run Export -impl impl_1
prj_run PAR -impl impl_1
prj_run Export -impl impl_1
#Stop recording: 3/15/2023 20:31:07



<A name="pn230315234707"></A><B><U><big>pn230315234707</big></U></B>
#Start recording tcl command: 3/15/2023 23:03:12
#Project Location: C:/Users/zyx/my_designs/awg_fpga; Project name: awg_fpga
prj_open "C:/Users/zyx/my_designs/awg_fpga/awg_fpga.rdf"
#Stop recording: 3/15/2023 23:47:07



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<LI><A href=#pn230315021019>pn230315021019</A></LI>
<LI><A href=#pn230315110431>pn230315110431</A></LI>
<LI><A href=#pn230315150526>pn230315150526</A></LI>
<LI><A href=#pn230315182402>pn230315182402</A></LI>
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